The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that enables the formation of a consistent shallow trench etch profile.
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-function devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices has been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) transistors, such as p-channel MOS (PMOS), n-channel MOS (NMOS) and complementary MOS (CMOS) transistors, bipolar transistors, BiCMOS transistors.
Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed. The particular structure of a given active device can vary between device types. For example, in MOS transistors, an active device generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions.
One important stage in the manufacture of such devices is the formation of isolation areas to electrically separate the electrical devices or portions thereof, that are closely integrated in the silicon wafer. While the particular structure of a given active device can vary between device types, a MOS-type transistor generally includes source and drain regions and a gate electrode that modulates current flowing in a channel between the source and drain regions. Unintended current should not flow between source and drain regions of adjacent MOS-type transistors. However, during the manufacturing process, movement of dopant atoms, for example, of boron, phosphorus, arsenic, or antimony, can occur within the solid silicon of the wafer. This movement is referred to as diffusion. The diffusion process occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to the silicon wafer and those dopant atoms within the silicon wafer. It is typically employed when forming p-type and n-type regions of a silicon integrated circuit device.
A technique referred to as xe2x80x9ctrench isolationxe2x80x9d has been used to limit such low. A particular type of trench isolation is referred to as shallow trench isolation (STI). STI is often used to separate the respective diffusion regions of devices of the same polarity type (i.e., p-type versus n-type).
In forming the STI regions one technique uses either silicon nitride (SiN) or photoresist to mask the etch. It is desirable to have a profile with nearly vertical trench sidewalls and that this profile, for all trench sidewalls, be consistent across the device and wafer. However, in practice, the profile is dependent upon the device topology. In regions with isolated lines (wide spaces), the STI profiles are less vertical or more tapered. On the other hand, those regions with dense lines (narrow spaces) are more vertical or less tapered.
In an example, prior art process using SiN, a desirable profile specification is in the range of about 80xc2x0xc2x13xc2x0. However, actual results indicate that the difference in slope between profiles in dense regions and isolated regions is about 7xc2x0, exceeding the specification.
FIG. 1A, illustrated in cross-section, depicts a region 100 having a pair of dense lines. Substrate 110 which has a thin oxide layer 120 and silicon nitride layer 130 thereon, has undergone a trench etch. The resulting profile 140 has an angle xcex1.
FIG. 1B depicts a region 105 in cross-section having a single isolated line. Substrate 115 having a thin oxide layer 125 and a nitride layer 135, has undergone a trench etch. The resulting profile 145 has an angle xcex8. Consequently, the angle xcex1 of FIG. 1A is smaller than the angle xcex8 of FIG. 1B, indicating a more vertical slope profile 140 of FIG. 1A with respect to the slope profile 145 of FIG. 1B.
Accordingly, there is a need for a process that ensures a more consistent STI profile not dependent upon the device topology and provides good critical dimension control from wafer to wafer, lot to lot.
The present invention provides for the manufacturing of shallow trench isolation that has consistent profile in regions of dense and isolated lines. Advantages realized include the attainment of nearly vertical profiles across the varying line density in a particular device and throughout the wafer substrate. In achieving nearly vertical profiles, the active devices designed critical dimensions, as intended by the circuit designer and drawn on the mask plates, may be more accurately translated into the silicon substrate during manufacturing than those attained with conventional processes. Consequently, the yield and performance of the manufactured devices is consistent across wafer.
The invention is exemplified in a number of implementations, two of which are summarized below. According to one embodiment, a method of forming trench isolation regions on a substrate comprises forming a dielectric stack on the substrate. This dielectric stack is made of a layer of silicon dioxide, a layer of silicon nitride, and a layer of a profile dielectric. A trench region is defined in the substrate through the dielectric stack.
In another embodiment, a method forms trench isolation regions on a silicon substrate. First, the method defines a dielectric stack. The dielectric stack is masked and coat ed with a photoresist and the photoresist is exposed to light. The dielectric stack is etched with a first etch forming a trench region in unmasked areas of the dielectric stack. The dielectric stack is etched until the silicon substrate is exposed. After first etch, the photoresist is removed. With a second etch, the trench region is etched again until a trench region of sufficient depth in the silicon substrate is defined.
The above summary of the present invention is not intended to represent each disclosed embodiment, or every aspect, of the present invention. Other aspects and example embodiments are provided in the figures and the detailed description that follows